1. Field of the Invention
This invention relates generally to the field of semiconductor device manufacturing and, more particularly, to a method and apparatus for enabling a timing synchronization circuit.
2. Description of the Related Art
Many high speed electronic systems possess critical timing requirements that dictate a need to generate a periodic clock waveform possessing a precise timing relationship with respect to some reference signal. The improved performance of computing integrated circuits and the growing trend to include several computing devices on the same board present a challenge with respect to synchronizing the time frames of all the components.
While the operation of all components in the system should be highly synchronized, i.e., the maximum skew in time between significant edges of the internally generated clocks of all the components should be minimized, it is not enough to feed the reference clock of the system to all the components. This is because different chips may have different manufacturing parameters, which, when taken together with additional factors such as ambient temperature, voltage, and processing variations, may lead to large differences in the phases of the respective chip generated clocks.
Conventionally, synchronization is achieved by using a timing circuit, such as a digital delay locked loop (DDLL) circuit, a clock synchronized delay (CSD) circuit, or a synchronous mirror delay (SMD) circuit to detect the phase difference between clock signals of the same frequency and produce a digital signal related to the phase difference. A common response in a synchronization circuit to high frequency noise is to generate a shift in one direction (i.e., to increase or decrease the delay), followed by a subsequent shift in the opposite direction (i.e., because the first shift was not representative of an actual phase difference between the input and output clocks). This undesirable shifting results in jitter in the output clock signal. This jitter in the output signal may reduce the stability of, or cause an error in, the digital device relying on the output clock.
DDLL circuits typically require a relatively large number of clock cycles to synchronize. As a result of this significant lock period, DDLL circuits are not typically disabled after a lock is achieved to conserve power. DDLL circuits are also not well suited to handling large temperature or voltage shifts due to their slow response time.
CSD and SMD circuits have been developed for providing a fast lock capability (e.g., within 1-4 clock cycles after initialization). One drawback of such circuits is noise sensitivity, which may result in considerable jitter due to process, voltage, and temperature (PVT) variations.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.